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Unknown serial EEPROM type. IIC %s Write Test. Enter Byte write address of IIC EEPROM (0-0x%x) 0x Address [0x%x] not valid. Input Write Characters (up to %d bytes) to terminate input %d bytes received : %02x Press any key to continue ... MAC address stored in EEPROM from [0x%x] to [0x%x] Ovewrite MAC address [Y/N] IIC Serial EEPROM %s write. Address=[0x%x]. Size=[0x%x]. IIC %s Read Test. Unknown serial EEPROM type. IIC %s Read Test Enter Byte Read address of IIC EEPROM (up to [0x%x]) Byte address [0x%x] not valid Input Read Data Size (up to [0x%x] bytes) Not correct data Size [0x%x] Read Data From IIC Serial EEPROM IIC Read/Write Test. Input pass count %d.IIC Read/Write Test Error Address [0x%x], Writed=[0x%02x], Read=[0x%02x], [0x%02x] Ok. Fail.Undefined Select IIC EEPROM. Current [%s] [1] AT24C01 ( 1K, 128 x 8). [2] AT24C02 ( 2K, 256 x 8). [4] AT24C04 ( 4K, 512 x 8). [8] AT24C08 ( 8K,1024 x 8). [0] AT24C16 (16K,2048 x 8). [A] Select device address. [Q] Quit. Select Item : Selected AT24C01 (1K,128x8). Selected AT24C02 (2K,256x8). Selected AT24C04 (4K,512x8). Selected AT24C08 (8K,1024x8). Selected AT24C16 (16K,2048x8). Serial EEPROM type = %s. Enter Device Address %d (0-7) In AT24C04 A0 used as a page address. In AT24C08 A0,A1 used as a page address. In AT24C08 A0,A1,A2 used as a page address. Device Address %d Invalid Device Address %c. Press Any Key to Continue Byte Write ACK not received. Dev 0x%02x. Byte Write ACK not received.Addr 0x%02x Byte Write ACK not received. Data 0x%02x Read Byte ACK not received. Dev 0x%02x. Read Byte ACK not received.Addr 0x%02x. Serial EEPROM %s (%dbytes)byte write & read test. Skip write EEPROM [Y/N] Random pattern [Y/N] Input pass count (%d) %d Write serial EEPROM... %d Read serial EEPROM... Error, address=[0x%x], write=[0x%02x], read=[0x%02x] Ok. Fail. Page write error. %d Reset IIC IICWrite error IIC read error. No ack %d Reset IIC Enter Byte Write address of IIC EEPROM (up to [0x%x]) Enter writed byte 0x Enter count of bytes (up to %d) 0x%02x IIC %s Test. Device Address %d [W] IIC Page Write Test. [R] IIC Sequential Read Test. [L] IIC Read/Write Test. [C] IIC Configuration View. [S] IIC EEPROM type & address Select. [B] IIC Byte Write. [D] IIC Byte Read. [T] IIC Byte Write & Read Test. [Q] Quit IIC Test Select Test Item : Press Any Key to Continue IIC Test IOPMOD Port Mode Register = 0x%08xP0 ........P1 ........P2 ........P3 ........P4 ........P5 ........P6 ........P7 ........P8 (xIRQ0)P9 (xIRQ1)P10 (xIRQ2)P11 (xIRQ3)P12 (DREQ0)P13 (DREQ1)P14 (DACK0)P15 (DACK1)P16 (TOEN0)P17 (TOEN1)P18 ()P19 ()P20 ()P21 ()P22 ()P23 ()P24 ()P25 ()\htȳԳ(4<DLT\dl %s..........1(output)0(input) IOPCON Port Control Register = 0x%08x %10s%15s%15s%10s%10sDetectionFilteringActiveEnable00(Level)01(Rising edge)10(Failing edge)11(Both edge)1(On)0(Off)1(high)0(low)1(enabled)0(disabled) xIRQ%d%5s%15s%15s%10s%10s1(Hight)0(Low) DREQ%d%5s%15s%15s%10s%10s1(enable) DACK%d%5s%15s%15s%10s%10s timeout0 for port 16 (TOEN0) .....................%s timeout1 for port 17 (TOEN1) .....................%s2 UART DCD0 or port21(DCD0)0(port2)3 UART CTS0 or port31(CTS0)0(port3)4 UART RTS0 or port41(RTS0)0(port4)5 UART DCD1 or port51(DCD1)0(port5)6 UART CTS1 or port61(CTS1)0(port6)7 UART RTS1 or port71(RTS1)0(port7)18 port18 or UART RxD01(RXD0)0(port18)19 port19 or UART DSR01(DSR0)0(port19)20 port20 or UART TxD01(TXD0)0(port20)21 port21 or UART DTR01(DTR0)0(port21)22 port22 or UART RxD11(RXD1)0(port22)23 port23 or UART DSR11(DSR1)0(port23)24 port24 or UART TxD11(TXD1)0(port24)25 port25 or UART DTR11(DTR1)0(port25) Type Esc to exit. Read or Write I/O Port data [R/W/Q] Write data to IOPDATA [5 hexdigit] 0x IOPDATA is writen 0x%08x IOPDATA is readed 0x%08x IOPMOD set to 0x%08x Set IOPDATA register [5 hexdigit] 0x IOPDATA 0x%08x xIRQ%d detection [0] Level detection. [1] Rising edge detection. [2] Failing edge detection. [3] Both edge detection. [Q] Quit. Select Item Filtering on [Y/N/Q] Active Hight [Y/N/Q] To set IOPDATA press [D] To break test press [Q] No external interrupts detected Detected %d external interrupts xIRQ%d configuration [Q] Quit from test. Filtering on [Y/N/Q] Active Hight [Y/N/Q] Enable xIRQ%d [Y/N/Q] DREQ%d Configuratuion DREQ%d Active Hight [Y/N/Q] DREQ%d Filtering on [Y/N/Q] DREQ%d Enable [Y/N] DACK%d Configuratuion DACK%d Active Hight [Y/N] DACK%d Enable [Y/N] P%d output [Y/N]ȳԳ( %s output [Y/N] [0] External Interrupt req 0 test. [1] External Interrupt req 1 test. [2] External Interrupt req 2 test. [3] External Interrupt req 3 test. [E] External Interrupt enable. [D] External Interrupt disable. [W] IOPDATA read/write. [S] Set port Mode & IOPCON. [M] IOPMOD Port Mode Register. [C] IOPCON Port Control Register. [O] IOPCON1 Port Control Register 1. [Q] Quit - Return main menu. Select test item Press any key to continue. Undefined Address : %08x Undefined Data : %08x Prefetch Abort Address : %08x Prefetch Abort Data : %08x Data Abort Address : %08x Data Abort Data : %08x ** Trap : SWI Handler [20] I2C interrupt[19] Ethernet MAC Rx int[18] Ethernet MAC Tx int[17] Ethernet BDMA Rx int[16] Ethernet BDMA Tx int[15] HDLCB Rx interrupt[14] HDLCB Tx interrupt[13] HDLCA Rx interrupt[12] HDLCA Tx interrupt[11] Timer 1 interrupt[10] Timer 0 interrupt[9] GDMA1 interrupt[8] GDMA0 interrupt[7] UART1 rx & error int[6] UART1 tx interrupt[5] UART0 rx & error int[4] UART0 tx interrupt[3] External interrupt 3[2] External interrupt 2[1] External interrupt 1[0] External interrupt 0 %c.%8d%8s INTMODE [0x%08x] = 0x%08x 1(FIQ)0(IRQ) INTPEND [0x%08x] = 0x%08x INTMASK [0x%08x] = 0x%08x[21] Global int mask bit Interrupt Status configurations. [F] INTMODE [0x%08x] = 0x%08x [P] INTPEND [0x%08x] = 0x%08x [M] INTMASK [0x%08x] = 0x%08x INTPRI0 [0x%08x] = 0x%08x INTPRI1 [0x%08x] = 0x%08x INTPRI2 [0x%08x] = 0x%08x INTPRI3 [0x%08x] = 0x%08x INTPRI4 [0x%08x] = 0x%08x INTPRI5 [0x%08x] = 0x%08x INTOFFSET[0x%08x] = 0x%08x [Q] Quit Select Item Press any key to continue.UndefPrefetchAbortSwiIrqFiq%8x Int sourcePRI [C] Change Int Priority [R] Read priority from regs INTPRI0-6 [W] Write priority to regs INTPRI0-6 Select Item Input Int source (0-%d) Incorrect Int source %d Selected %s Input Int priority (0-%d) Incorrect Int priority %d1(Fiq)0(Irq) [C] Change Int Mode Input Int source (0-%d) INTERRUPT TEST [V] View the interrupt configuration. [S] View Interrupt statistics. [C] Clear Interrupt statistics. [P] Set Interrupt Priority. [M] Set Interrupt Mode. [Q] Type Q for exit interrupt test. Select Test Item: Error Report MAC Tx Count...........%8d Transmit collission ...%8d Transmit deferred......%8d Paused.................%8d Underrun...............%8d Deferral...............%8d No carrier.............%8d Signal quality error...%8d Late collision.........%8d Transmit parity error..%8d Transmission halted....%8d Control frame received.%8d Receive 10-Mb/s status.%8d Alignment error........%8d CRC error..............%8d Overflow error.........%8d Long error.............%8d Receive parity error...%8d Reception halted ......%8d BDMA Tx null list......%8d BDMA Tx not owner......%8d BDMA Tx buffer empty...%8d BDMA Received good.....%8d BDMA Rx null list......%8d BDMA Rx not owner......%8d BDMA Rx max size over..%8d Missed Error Count.....%8d 0.Control Register : 0x%04x 0.15 [R] Reset (R/W/SC) ...................%s1(Reset chip)0(Enable normal operation) 0.14 [L] Loopback mode (R/W) ..............%s1(Enable loopback mode)0(Disable loopback mode) 0.13 [S] Speed Selection (R/W) ............%s1(100Mbps)0(10Mbps) 0.12 [A] Auto-Negotiation Enable (R/W) ....%s1(Enable auto-negotiate process)0(Disable auto-negotiate process) 0.11 [P] Power Down (R/W) .................%s1(Enable power down) 0.10 [I] Isolate (R/W) ....................%s1(Electrically isolate from MII)0(Normal operation) 0.9 [N] Restart Auto-Negotiation (R/W/SC) %s1(Restart AN) 0.8 [F] Duplex mode (R/W) ................%s1(Enable full-duplex)0(Disable full-duplex) 0.7 [C] Colision Test (R/W) ..............%s1(Enable COL signal test)0(Disable COL signal test) 0.6:0.4 Transceiver Test Mode (RO) .......%d(Not Supported) 0.3 Master-Slave Enable (RO) .........%s1(Enable)0(Disable) 0.2 Master-SlaveValue (RO)............%s10 R/W = Read/Write. SC = Self Clearing. [Q] Quit PHY Control Register Test. Select Test Item : Reset PHY [Y/N/Q] Reseting PHY... Enable loopback mode [Y/N/Q] Loopback mode enabled. Loopback mode disabled. Speed Selection. Enable 100Mbps [Y/N/Q] Selected speed 100Mbps. Selected speed 10Mbps. Auto-Negotiation Enable [Y/N/Q] Auto-Negotiation Enabled. Auto-Negotiation Disabled. Power Down [Y/N/Q] Power down enabled. Power down disabled. Electrically Isolate PHY from MII [Y/N/Q] PHY Electrically isolated from MII. PHY connected to MII. Restart Auto-Negotiation [Y/N/Q] Auto-negotiation restarted. Full-Duplex mode [Y/N/Q] Full-duplex enabled. Full-duplex disabled. Colision Test [Y/N/Q] Colision Test enabled. Bit 0.14 must be enabled to use this bit. This bit is used in conjunction with bit 0.14 to test the COL output. Colision Test disabled. Invalid Test Item Selected Press any key to continue 1. Status Register : 0x%04x 1.15 100BASE-T4 (RO).....................%s1(Supported)0(Not Supported 1.14 100BASE-X full-duplex (RO)..........%s0(Not Supported) 1.13 100BASE-X half-duplex (RO)..........%s 1.12 10 Mb/s full-duplex (RO)............%s 1.11 10 Mb/s half-duplex (RO)............%s 1.10 100BASE-T2 full-duplex (RO).........%s 1.9 100BASE-T2 half-duplex (RO).........%s 1.7 Master-Slave Configuration Fault....%s 1.6 MF Preamble Suppression (RO)........%s 1.5 Auto-Negotiation Complete (RO)......%s1(Auto-negotiation process complete)0(Auto-negotiation process not complete) 1.4 Remote Fault (RO/LH)................%s1(Remote fault condition detected)0(No remote fault condition detected) 1.3 Auto-Neg. Ability (RO)..............%s 1.2 Link Status (RO/LL).................%s1(Link is up)0(Link is down) 1.1 Jabber Detect(10BASE-TOnly)(RO/LH)..%s1(Jabber condition detected0(No jabber condition detected) 1.0 Extended Register Capability (RO)...%s0(No Supported) RO = Read Only LL = Latching Low LH = Latching High PHY.2,3 Identification Registers 1,2. 2.PHY identififcation Register 1 ......0x%04x 2.15:0 bit 3 througt 18 of OUI ......0x%04x Register bit number .%2d bit value ........... OUI bit number ...... 3.PHY identififcation Register 2 ......0x%04x 3.15:10 bits 19 throught 24 of the OUI.0x%04x 3.9 : 4 Manufactures Part Number.......0x%x 3.3 : 0 Manufactures revision Number...0x%x OUI............................0x%06x 4.Auto Negotiation Advertisement Register : 0x%04x 4.15 Next Page (RO)...............%s 4.13 [F] Remote Fault (R/W)...........%s1(Remote fault)0(No remote fault) 4.12:11 Reserved Ignore on read(R/W).%d%d 4.10 [P] Pause (R/W) .................%s1(Pause operation is enabled for full-duplex links)0(Pause operation is disabled) 4.9 [A] 100BASE-T4 (R/W).............%s1(100BASE-T4 capability is available)0(100BASE-T4 capability is not available) 4.8 [B] 100BASE-TX full-duplex (R/W).%s1(DTE is 100BASE-TX full-duplex capable)0(DTE is not 100BASE-TX full-duplex capable) 4.7 [C] 100BASE-TX (R/W).............%s1(DTE is 100BASE-TX capable)0(DTE is not 100BASE-TX capable) 4.6 [D] 10BASE-T full-duplex (R/W)...%s1(DTE is 10BASE-T full-duplex capable)0(DTE is not 10BASE-T full-duplex capable) 4.5 [E] 10BASE-T (R/W)...............%s1(DTE is 10BASE-T capable)0(DTE is not 10BASE-T capable) 4.4:0[S] Selector Filed (R/W).........<00001> = IEEE 802.3<00010> = IEEE 802.9 ISLAN-16T<00000> = Reserved for future Auto-Negotiation development<11111> = Reserved for future Auto- Negotiation development%x R/W = Read/Write RO = Read Only [Q] Quit Enable Remote Fault [Y/N/Q] Remote Fault Enabled. Remote Fault Disabled. Enable Pause operation for full-duplex links [Y/N/Q] Pause operation is enabled for full-duplex links. Pause operation is disabled. The LXT970A does not support 100BASE-T4, but allows this bit to be set to advertise in the Auto-Negotiation sequence for 100BASE-T4 operation. An external 100BASE-T4 transceiver could be switched in if this capability is desired. Enable 100BASE-T4 capability [Y/N/Q] 100BASE-T4 capability is available. 100BASE-T4 capability is not available. Enable 100Base-TX full-duplex [Y/N/Q] DTE is 100Base-TX full-duplex capable. DTE is not 100BASE-TX full-duplex capable. Enable 100Base-TX [Y/N/Q] DTE is 100BASE-TX capable. DTE is not 100BASE-TX capable. Enable 10Base-T full-duplex [Y/N/Q] DTE is 10BASE-T full-duplex capable. DTE is not 10BASE-T full-duplex capable. Enable 10Base-T [Y/N/Q] DTE is 10BASE-T capable. DTE is not 10BASE-T capable. Selector Filed. [1] <00001> = IEEE 802.3. [2] <00010> = IEEE 802.9 ISLAN-16T. [0] <00000> = Reserved for future Auto-Negotiation development. [R] <11111> = Reserved for future Auto-Negotiation development. [Q] Quit Selector Field = <00001>(IEEE 802.3). Selector Field = <00010>(IEEE 802.9 ISLAN-16T). Selector Field = <00000>. Selector Field = <11111>. 5.Auto Negotiation Link Partner Ability : 0x%04x 5.15 Next Page (RO)............%s1(LP has ability to send multiple pages)0(LP has no ability to send multiple pages) 5.14 Acknowledge (RO)..........%s1(LP has received Link Code Word)0(LP has not received Link Code Word) 5.13 Remote Fault (RO).........%s 5.10 Pause (RO)................%s1(Pause operation is enabled for LP)0(Pause operation is disabled for LP) 5.9 100BASE-T4 (RO)...........%s1(LP is 100BASE-T4 capable)0(LP is not 100BASE-T4 capable) 5.8 100BaseTX full-duplex(RO).%s1(LP is 100BASE-TX full-duplex capable)0(LP is not 100BASE-TX full-duplex capable) 5.7 100BASE-TX (RO)...........%s1(LP is 100BASE-TX capable)0(LP is not 100BASE-TX capable) 5.6 10BASE-T full-duplex(RO)..%s1(LP is 10BASE-T full-duplex capable)0(LP is not 10BASE-T full-duplex capable) 5.5 10BASE-T (RO).............%s1(LP is 10BASE-T capable)0(LP is not 10BASE-T capable) 5.4:0 Selector Field (RO)......<00001>(IEEE 802.3)<00010>(IEEE 802.9 ISLAN-16T)<00000>(Reserved for future Auto-Negotiation development)<11111>(Reserved ved for future Aut o-Negotiation development) LP = Link Partner 6. Auto Negotiation Expansion Register : 0x%04x 6.4 Parallel Detect.Fault (RO/LH).%s1(Parallel detection fault has occurred)0(Parallel detection fault has not occurred) 6.3 LP Next Page Able (RO)........%s1(Link partner is next page able)0(Link partner is not next page able) 6.2 Next Page Able (RO)...........%s 6.1 Page Received (RO/LH).........%s1(3 identical and consecutive link code words received)0(3 identical and consecutive link code words not received) 6.0 LP Auto Neg Able (RO).........%s1(LP is auto-negotiation able)0(LP is not auto-negotiation able) LP = Link Partner RO = Read Only LH = Latching High PHY.16. Read/Write test 16. Mirror Register : 0x%04x This register is intended for use in checking the MII serial port and has no affect on chip operation. Press any key to run read & write test Press any key to break read & write test PHY_ECNTL_REG1 Write Error Time %d:%d:%d.%d Fail. Ok. 17.Interrupt Enable Register : 0x%04x 17.3 [L] MII driver levels(R/W)...%s1(Reduced MII driver levels)0(High-strength MII driver levels) 17.2 [C] Link Loss Criteria(R/W)..%s1(Enhanced link loss criteria)0(Standard link criteria) 17.1 [E] Enable interrupts(R/W)...%s1(Enable interrupts)0(Disable interrupts) 17.0 [T] TINT(R/W)................%s1(Forces MDINT Low and sets bit 18.15 = 1) Reduced MII driver levels [Y/N/Q] Reduced MII driver levels. High-strength MII driver levels. Enhanced link loss criteria. Link loss criteria is independent of symbol error rate. Loss of scrambler lock for more than 1 - 2 msec will brings the link down. Link up criteria is based on symbol error rate. Standard link criteria. Both link up and link loss are based on symbol error rate. Enable Enhanced link loss criteria [Y/N/Q] Enhanced link loss criteria. Standard link criteria Enable interrupts [Y/N/Q] Enable Interrupts. Disable interrupts. Force MDINT Low and set bit 18.15 = 1 [Y/N/Q] Force MDINT Low and sets bit 18.15 = 1. Normal operation. 18.Interrupt Status Register : 0x%04x 18.15 MINT (RO)....%s1(MII interrupt pending)0(no MII interrupt pending) 18.14 XTAL OK (RO).%s1(LXT970A powered up and the on-chip clocks are stable)0(XTAL circuit is not stable) RO = Read Only 19. Configuration Register : 0x%04x 19.14 [T] Txmit Test(100BASE-TX)(R/W)...%s1(100BASE-T transmit test enabled) 19.13 [R] Repeater Mode (R/W)...........%s1(Enable Repeater Mode)0(Enable DTE Mode) 19.12 [M] MDIO_INT (R/W)................%s1(Enable interrupt signaling on MDIO) 19.11 [P] TP Loopback(10BASE-T)(R/W)....%s1(Disable 10Base TP Loopback)0(Enable 10Base TP Loopback) 19.10 [E] SQE (10BASE-T) (R/W)..........%s1(Enable SQE)0(Disable SQE) 19.9 [J] Jabber (10BASE-T)(R/W)........%s1(Disable jabber) 19.8 [L] Link Test (10BASE-T)(R/W).....%s1(Disable 10BASE-T link integrity test). 19.7:6[C] LEDC Programming bits(R/W)....00 LEDC indicates collision01 LEDC is off10 LEDC indicates activity11 LEDC is continuously on 19.5 [A] Advance TX Clock(R/W).........%s1(TX clock is advanced relative to TXD<4:0> and TX_ER by 1/2 TX_CLK cycle) 19.4 [5] 5B Symbol/4B Nibble(100BASEX).%s1(5-bit Symbol Mode)0(4-bit Nibble Mode) 19.3 [S] Scrambler(100BASEX only)(R/W).%s1(Bypass Tx scrambler & Rx descrambler)0(Scrambler and descrambler enabled) 19.2 [F] 100BASE-FX(R/W)...............%s1(Enable 100BASE fiber interface)0(Disable fiber interface) 19.0 [D] Transmit Disconnect(R/W)......%s1(Disconnect TP transmitter from line) [Q] Quit If Txmit Test enabled LXT970A transmit data regardless of link status Txmit Test(100BASE-TX) [Y/N/Q] Txmit 100BASE-TX Test Enabled. Txmit 100BASE-TX Test Disabled. Enable Repeater Mode [Y/N/Q] Repeater Mode Enabled. Repeater Mode Disabled (Enable DTE Mode). Enable interrupt signaling on MDIO [Y/N/Q] Interrupt signaling on MDIO enabled. Bit is ignored unless the interrupt function is enabled (17.1=1). Normal operation (MDIO interrupt disabled). Enable TP Loopback(10BASE-T) [Y/N/Q] TP Loopback(10BASE-T) Enabled. TP Loopback(10BASE-T) Disabled. Enable SQE (10BASE-T) [Y/N/Q] SQE (10Base-T) Enabled. SQE (10Base-T) Disabled. Disable Jabber (10BASE-T) [Y/N/Q] Jabber 10Base-T disabled. Normal operation. Jabber 10Base-T enabled. Disable 10BASE-T link integrity test [Y/N/Q] 10BASE-T Link Integrity test disabled. 10BASE-T Link Integrity test enabled. LEDC Programming bits. [C] LEDC indicates collision. [F] LEDC is off. [A] LEDC indicates activity. [N] LEDC is continuously on. LEDC indicates collision. LEDC is off. LEDC indicates activity. LEDC is continuously on. Invalid Item Selected Enable Advanced TX Clock [Y/N/Q] TX clock is advanced relative to TXD<4:0>,TX_ER by 1/2 TX_CLK cycle. Enable 100BASE-X 5B Symbol mode [Y/N/Q] 5-bit Symbol Mode seted. 4-bit Nibble Mode seted. Bypass transmit scrambler and receive descrambler (100BASE-X only) [Y/N/Q] Bypass transmit scrambler and receive descrambler. Normal operation (scrambler and descrambler enabled). Enable 100Base fiber interface [Y/N/Q] 100Base fiber interface enabled. Fiber interface disabled. 100Base twisted-pair interface enabled. Disconnect TP transmitter from line [Y/N/Q] TP transmitter disconnected from line. 20. Chip Status Register : 0x%04x 20.13 Link(RO).........................%s 20.12 Duplex Mode(RO)..................%s1(Full-duplex)0(Half-duplex) 20.11 Speed(RO)........................%s1(100 Mbps operation)0(10 Mbps operation) 20.9 Auto-Negotiation Complete(RO/LH).%s 20.8 Page Received(RO/LH).............%s1(Three identical and consecutive link code words received0(Three identical and consecutive link code words not received 20.2 Low-Voltage(RO)..................%s1(Low-voltage fault on VCC has occurred)0(No fault) STACON 15:13 MDC clock rating......%d (%d x 1/fMCLK) [0] 000 16 x (1/fMCLK) [1] 001 18 x (1/fMCLK) [2] 010 20 x (1/fMCLK) [3] 011 22 x (1/fMCLK) [4] 100 24 x (1/fMCLK) [5] 101 26 x (1/fMCLK) [6] 110 28 x (1/fMCLK) [7] 111 30 x (1/fMCLK) Select MDC Clock Rate MDC Clock Rate is fMCLK / %d = %d MDC Offed 4:0 PHY register address (Addr).%d 9:5 PHY address (PHY)...........%d 10 Write (Wr)..................%d 11 Busy bit (Busy).............%d 12 Preamble suppress (PreSup)..%d 15:13 MDC clock rating............%d fMCLK / ([15:13] * 2 + 16)..%d PHY Station Management. [C] Read & Write PHY.0 Control Register. [S] Read PHY.1 Status Register. [D] Read PHY.2,3 Identification Registers 1,2. [A] Read & Write PHY.4 Auto Negotiation Advertisement Register. [P] Read PHY.5 Auto Negotiation Link Partner Ability Register. [N] Read PHY.6 Auto Negotiation Expansion Register. [W] Read & Write PHY.16 test. [I] Read & Write PHY.17 Interrupt Enable Register. [M] Read PHY.18 Interrupt Status Register. [E] Read & Write PHY.19 Extended control register. [R] Read PHY.20 Chip Status Register. [T] STACON Register. [O] MDC On Test [F] MDC Off Test MACCON (MAC Gloabal Control Register) = 0x%08x 0 Halt request (HaltReq)...........%s1(Stop Tx & Rx) 1 Halt immediate (HaltImm).........%s1(Stop Tx & Rx immediately) 2 Software reset (Reset)...........%s 3 Full-duplex (FullDup)............%s1(Full Duplex Supported)0(Half Duplex Supported) 4 MAC loopback (MACLoop) ..........%s 6 MII-OFF..........................%s1(10M bits/s interface selected)0(MII selected) 7 Loop 10 Mb/s (Loop10)............%s 10 Missed roll (MissRoll)...........%s1(error counter rolls over) 12 MDC-OFF .........................%s1(MII Station Management Clock Off)0(MDC Clock generation enabled) 13 Enable missed roll (EnMissRoll)..%s1(Enable MissRoll interrupt)0(Disable MissRoll interrupt) 15 Link status 10 Mb/s (Link10).....%s MACTXCON : MAC Tx Control Register = 0x%08x 0 MAC Tx (TxEn).......................%s1(Enabled)0(Disabled) 1 Transmit Halt Request (TxHalt)......%s1(Transmit halted)) 2 Suppress Padding (NoPad)............%s1(no generate pad bytes) 3 Suppress CRC (NoCRC)................%s1(No generate CRC) 4 Fast Back-off (FBack)...............%s 5 Disable the defer counter (NoDef)...%s 6 Send Pause (SdPause)................%s 7 MII 10-Mb/s SQE test mode en.(SQEn).%s 8 Enable Underrun (EnUnder)...........%s1(enabled)0(disabled) 9 Enable Deferral (EnDefer)...........%s 10 Enable NoCarrier (EnNCarr)..........%s 11 En. Excessive Collision (EnExColl)..%s 12 Enable Late Collision (EnLateColl)..%s 13 FIFO Parity Error (EnTxPar).........%s 14 Packet Tx Complete (EnComp).........%s MACRXCON : MAC Receive Control Register = 0x%08x 0 MAC Rx Enabled (RxEn)..............%s 1 Receive Halt Requested (RxHalt)....%s1(Halt Rx after current packet) 2 MAC Rx Long Frame(1518B)(LongEn)...%s 3 MAC Rx Short Frame(64B)(ShortEn)...%s 4 Strip CRC (StripCRC)...............%s0(disabled 5 Rx Pass Control Packet (PassCtl)...%s 6 MAC Rx Ignore CRC (IgnoreCRC)......%s1(disable CRC checking)0(enable CRC checking) MAC Rx Interrupt : 8 Mis-Allign Interrupt (EnAlign).....%s 9 CRC Error Interrupt (EnCRCErr).....%s 10 FIFO Overflow Interrupt (EnOver)...%s 11 Over 1518B Frame Int. (EnLongErr)..%s 13 Parity Error Interrupt (EnRxPar)...%s 14 Rx Good Interrupt(EnGood)..........%s %s MAC Transmit Status Register = 0x%08x 3:0 Transmit collision count (TxColl)...%d4 Excessive collision (ExColl)........5 Transmit deferred (TxDeferred)......6 Paused (Paused).....................7 Interrupt on transmit (IntTx).......8 Underrun (Under)....................9 Deferral (Defer)....................10 No carrier (NCarr)..................11 Signal quality error (SQE)..........12 Late collision (LateColl)...........13 Transmit parity error (TxPar).......14 Completion (Comp)...................15 Transmission halted (TxHalted)...... MAC Receive Status Register = 0x%08x5 Control frame received (CtlRecd)..6 Interrupt on receive (IntRx)......7 Receive 10-Mb/s status (Rx10Stat).8 Alignment error (AlignErr)........9 CRC error (CRCErr)................10 Overflow error (overflow).........11 Long error (LongErr)..............13 Receive parity error (RxPar)......14 Good received (Good)..............15 Reception halted (RxHalted)....... CAMCON. CAM Control Register = 0x%08x 0 Accept Unicast station address packet(StationAcc)...%s 1 Accept Multicast-group address packet(GroupAcc).....%s 2 Accept Broadcast station address(BroadAcc)..........%s 3 Accept Negative CAM recognizes(NegCAM)..............%s 4 CAM Compare Enable mode(CompEn).....................%s CAMEN. CAM Enable Register = 0x%08x %2d CAM Entry ......1(is valid)0(not valid) EPZCNT. MAC Received Pause Count Register = 0x%08x [15:0] Number of time slots the transmitter was paused due to the receipt of control Pause operation packet from the MAC. ERMPZCNT. MAC Remote Pause Count Register = 0x%08x [15:0] Number of time slots that a remote MAC was paused as a result of sending control Pause operation packets. BDMATXCON : BDMA Tx Control Register=0x%08x 4:0 BDMA Tx Burst Size........................%d Words 5 BDMA Tx Stop/Skip (TxSTSKO)...............%s1(BDMA Tx STOP)0(BDMA Tx SKIP) 7 Control Packet Tx Complete int.(TxCPIE)...%s 8 BDMA Tx Null list interrupt (TxNLIE)......%s 9 BDMA Tx Not Owner interrupt (TxNOIE)......%s 10 BDMA Tx Buffer Empty interrupt (TxEmpty)..%s 13:11 BDMA Tx to MAC Tx Start Level.............%d(%d/8 BDMA buffer) 14 BDMA Tx (TxEn)............................%s 15 BDMA Tx Reset (TxRS)......................%s BDMARXCON : BDMA Receive Control Register = 0x%08x 4:0 BDMA Rx Burst Size ............................%d Words 5 BDMA Rx Stop/Skip Frame by owner bit(BRxSTSKO).%s1(STOP if not owner)0(SKIP if not owner) 6 BDMA Rx Memory Address Inc/Dec (RxMAINC).......%s1(increment)0(decrement) 7 BDMA Rx Every Received Frame Interrupt(RxDIE)..%s1(enable)0(disable) 8 NULL List Interrupt (RxNLIE)...................%s 9 BDMA Rx Not Owner Interrupt (RxNOIE)...........%s 10 BDMA Rx Maximum Size over Interrupt (RxMSOIE)..%s 11 BDMA Rx Big/Little Endian (RxLittle)...........%s1(Little)0(Big) 13:12 BDMA Rx Word Allignment (RxWA)...............00(no invalid bytes)01(one invalid byte)10(two invalid bytes)10(three invalid bytes) 14 BDMA Rx Enable (RxEn)..........................%s 15 BDMA Rx Reset (RxRS)...........................%s 16 BDMA Rx Buffer Empty Interrupt (RxEmpty).......%s 17 BDMA Rx Early notify Interrupt (RxEarly).......%s BDMASTAT : BDMA Status Register = 0x%08x0 BDMA Rx done every received frame (BRxRDF)1 BDMA Rx null list (BRxNL)2 BDMA Rx not owner (BRxNO)3 BDMA Rx maximum size over (BRxMSO)4 BDMA Rx buffer empty (BRxEmpty)5 Early notification (BRxSEarly)7 One more frame data in BDMA Rx buffer(BRxFRF)15:8 Number of frames in BDMA receive buffer (BRxNFR)%d16 BDMA Tx complete to send control packet (BTxCCP)17 BDMA Tx null list (BTxNL)18 BDMA Tx not owner (BTxNO)20 BDMA Tx buffer empty (BTxEmpty) BDMATXPTR BDMA Transmit Frame Descriptor Start Address Register 25:0 BDMA transmit frame descriptor start address = 0x%08x BDMARXPTR BDMA Receive Frame Descriptor Start Address Register 25:0 BDMA receive frame descriptor start address = 0x%08x BDMARXLSZ Receive Frame Maximum Size Register. 15:0 BDMA receive frame maximum size (BRxLSZ).%d 31:16 BDMA receive frame length (BRxFSZ).......%d BDMA Tx/Rx and CAM Buffer Test BDMA Tx Buffer Test. Base Address = 0x%08x. Size=64 words... BDMA Tx Buffer Error [0x%08x]=0x%08x, must =0x%08xOk.Fail. BDMA Rx Buffer Test. Base Address = 0x%08x. Size=64 words.... BDMA Rx Buffer Error [0x%08x]=0x%08x, must =0x%08x CAM Read/Write Test. Base Address = 0x%08x.Size=32 words.... BDMATXCON BDMA Tx Control Register Setup BDMA Tx Burst Size (TxBRST)..................%d BDMA Tx STOP when Descr.Not Owner (BTxSTSKO).%s BDMA Tx to MAC Tx Start Level (BTxMSL).......%dNo wait to fill the BDMAwait to fill 1/8 BDMAwait to fill 2/8 BDMAwait to fill 3/8 BDMAwait to fill 4/8 BDMAwait to fill 5/8 BDMAwait to fill 6/8 BDMAwait to fill 7/8 BDMA BDMA Tx Interrupt Setting Control Packet Tx Complete Int (BTxCPIE).....%s BDMA Tx Descriptor Not Owner Int.(BTxNOIE)...%s BDMA Tx Buffer Empty Interrupt (BTxEmpty)....%s BDMA Tx Null List Interrupt enable (BTxNLIE).%s Change BDMATXCON [Y/N] Input BDMA Tx Burst Size (TxBRST)............ BDMA Tx STOP when Descriptor Not Owner [Y/N] Input BDMA Tx to MAC Tx Start Level (BTxMSL) Control Packet Tx Complete Int (BTxCPIE)[Y/N] BDMA Tx Descriptor Not Owner Interrupt [Y/N] BDMA Tx Buffer Empty Int (BTxEmpty) [Y/N] BDMA Tx Null List Interrupt (BTxNLIE) [Y/N] BDMARXCON BDMA Rx Control Register Setup BDMA Rx Burst Size (BRxBRST).................%d BDMA Rx STOP when Descr.Not Owner (BRxSTSKO).%s1(stop)0(skip) BDMA Rx Memory Increment (BRxMAINC) .........%s BDMA Rx Memory Little-Endian (RxLittle)......%s1(little)0(big) BDMA Rx Interrupt Setting Every Received Frame Interrupt (BRxDIE)......%s Null List Interrupt .........................%s Descriptor Not Owner Interrupt (BRxNOIE).....%s Maximum Size Over Interrupt (BRxMSOIE).......%s BDMA Rx Buffer Empty Interrupt ..............%s Early Notify Interrupt ......................%s Change BDMARXCON [Y/N] Input BDMA Rx Burst Size (BRxBRST) BDMA Rx STOP when Descriptor Not Owner [Y/N] BDMA Rx Memory Increment (BRxMAINC) [Y/N] BDMA Rx Memory Little-Endian (RxLittle) [Y/N] Every Received Frame Interrupt (BRxDIE) [Y/N] Null List Interrupt (BRxNLIE) [Y/N] Descriptor Not Owner Interrupt (BRxNOIE)[Y/N] Maximum Size Over Interrupt (BRxMSOIE) [Y/N] BDMA Rx Buffer Empty Interrupt(RxEmpty) [Y/N] Early Notify Interrupt (BRxEarly) [Y/N] BDMA Configuration. [R] BDMARXCON BDMA Receive Control Register. [T] BDMATXCON BDMA Transmit Control Register. [S] BDMASTAT BDMA Status Register. [P] BDMAPTR BDMA Rx & Tx Frame Descriptor Start Address Registers. [M] BDMARXLSZ BDMA Receive frame maximum size. [B] BDMA Rx/Tx & CAM Buffers Test. [C] Change BDMA Configuration. [Q] Quit. Press any key to Continue Change MAC Address Read MAC Address from serial EEPROM [Y/N] MAC Adress = %02x Change MAC Address [Y/N] Input MAC Address : %X Write MAC Address %02x to serial EEPROM [Y/N] MACCON Global Control Register Support Full Duplex (FullDup)...................%s Use 10Mbps 7-Wire Interface (MIIOFF)............%s Missed Error Count Over Interrupt (EnMissRoll)..%s Change MACCON [Y/N] Support Full Duplex (FullDup) [Y/N] Use 10Mbps 7-Wire Interface (MIIOFF) [Y/N] Missed Error Count Over Interrupt [Y/N] MACTXCON MAC Tx Control Register Setup MAC Tx No Padding (NoPad).......................%s1(enabled) MAC Tx No CRC (NoCRC)...........................%s MAC Tx Use Fast Back-off timers (FBack).........%s MAC Tx Disable the Defer Counter (NoDef)........%s(1)(0) MAC Tx Interrupt Setting Underrun Interrupt (EnUnder)....................%s Deferral Interrupt (EnDefer)....................%s No Carrier Interrupt (EnNCarr)..................%s Excessive Collision Interrupt (EnExColl)........%s Late Collision Interrupt (EnLateColl)...........%s Parity Error Interrupt (EnTxPar)................%s Change MACTXCON [Y/N] MAC Tx No Padding (NoPad) [Y/N] MAC Tx No CRC (NoCRC) [Y/N] MAC Tx Use Fast Back-off timers (FBack) [Y/N] MAC Tx Disable the Defer Counter (NoDef) [Y/N] Enable Underrun Interrupt (EnUnder) [Y/N] Enable Deferral Interrupt (EnDefer) [Y/N] Enable No Carrier Interrupt (EnNCarr) [Y/N] Enable Late Collision Interrupt(EnLateColl)[Y/N] Enable Parity Error Interrupt (EnTxPar) [Y/N] Excessive Collision Interrupt (EnExColl) [Y/N] MACRXCON MAC Rx Control Register Setup MAC Rx Long Frame Enable (LongEn)...............%s MAC Rx Short Frame Enable (ShortEn).............%s MAC Rx Strip CRC (StripCRC).....................%s MAC Rx Pass Control Packet (PassCtl)............%s MAC Rx Ignore CRC Check (IgnoreCRC).............%s MAC Rx Interrupt Setting Mis-Allign Interrupt (EnAlign)..................%s CRC Error Interrupt (EnCRCErr)..................%s FIFO Overflow Interrupt (EnOver)................%s Long Frame Interrupt (EnLongErr)................%s Parity Error Interrupt (EnRxPar)................%s Change MACRXCON [Y/N] MAC Rx Long Frame Enable (LongEn) [Y/N] MAC Rx Short Frame Enable (ShortEn) [Y/N] MAC Rx Strip CRC (StripCRC) [Y/N] MAC Rx Pass Control Packet (PassCtl) [Y/N] MAC Rx Ignore CRC Check (IgnoreCRC) [Y/N] Enable Mis-Allign Interrupt (EnAlign) [Y/N] Enable CRC Error Interrupt (EnCRCErr) [Y/N] Enable FIFO Overflow Interrupt (EnOver) [Y/N] Enable Long Frame Interrupt (EnLongErr) [Y/N] Enable Parity Error Interrupt (EnRxPar) [Y/N] Accept Unicast Station Address (StationAcc).....%s Accept Multicast-Group Station Address(GroupAcc)%s Accept Broadcast Station Address (BroadAcc).....%s Accept Negative CAM Reconization (NegCAM).......%s Configure CAM (Y/N) ? Accept Unicast Station Address (StationAcc)[Y/N] Accept Multicast-Group Station Address [Y/N] Accept Broadcast Station Address [Y/N] Accept Negative CAM Reconization (NegCAM) [Y/N] MAC Configuration. [C] MACCON MAC Global Control Register. [T] MACTXCON MAC Transmit Control Register. [R] MACRXCON MAC Receive Control Register. [S] MACTXSTAT MAC Transmit Status Register. [E] MACRXSTAT MAC Receive Status Register. [A] CAMCON CAM Control Register. [N] CAMEN CAM Enable Register. [P] EPZCNT MAC Received Pause Register. [Z] EPRMZCNT MAC Remote Pause Register. [H] MAC Configuration Change. Dest Address:Source Address : Length (%d,0x%x). Type & Length : CRC Value:%02x Tx Packet Count %d Input Tx Packet Count (default 10000) Random packet length & filling [Y/N] Input packet data length (default 1500) MAC Loopback Test is Running (send %d packets) ... Packets data length=%d #=%d packets sended. To break test press [Q]. [S] to stop Rx # Err frame length. Tx length=%d, Rx length=%d Mismatch Frame (Frame Num=%d)... Frame length error. Wait Rx num=%d, Tx length=%d, Rx length=%d Dest Addr Err: Src Addr Err: Frame type & length filed error 0x%02x 0x%02x Sequense number error. Wait %d. Recv %d Frame filling error Total Tx Frames %d bytes %d, %d bytes/sec, Rx Frames %d Ok. Fail. Total Mismatch Frame is %d. MAC Internal Loopback Test MAC - PHY LoopBackTest(Without Collision) Set PHY mode : Full-Duplex, 100Mb, Loop Back Reset PHY MAC - PHY LoopBackTest(With Collision) Set PHY mode : 100Mb, Loop Back, Collision Test All LoopBackTest(Without Physical LoopBack) MAC LoopBack Test [I] MAC Internal LoopBackTest [L] MAC - PHY LoopBackTest(Without Collision) [C] MAC - PHY LoopBackTest(WithCollision) [E] Physical Ethernet LoopBackTest [A] All LoopBackTest(Without Physical LoopBack) [Q] Quit MAC LoopBack Test Receive MAC Frame. Print Received Frames [Y/N] Waiting For Frame Receive [Q/q] Rx frames=%d, bytes=%d, %d bytes/sec Select Transmit(T) or Quit(Q) Send MAC Frame error. Transfer Multiple MAC Frame. #=100 packets sended. Press any key to break test Send MAC Packet Error Sended %d Packets. Transfer MAC Frame [S] Transfer Single MAC Frame [M] Transfer Multiple MAC Frame [C] Transfer Control Frame [Q] Quit MAC Transfer Test MAC Tx Halt Request Test Select (Q)uit or (T)x 2 Frame : Buffer empty Show Received Frame Data(%d Frames) [A] Show All Received Frame. [N] Show by Rx Sequence. [L] Show by Rx Frame Length. [S] Show by Source Address. [D] Show by Destination Address. [C] Show Control Frame. Select Item Enter Sequence Number : Enter Rx Frame Length : Enter Source Address : Enter Destination Address : Incorrect capture buffer structure. %d'th Received Frame Data, status = %x Received Time: %d min %d sec %d'th Received Frame Data(%x) +++ %d'th Frame is Less than %d Byte, status %x Received Time: %d min %d sec %d'th Frame is Source Address Mached(%x) %d'th Frame is Destination Address Mached(%x) %d'th Frame is Control Frame(%x) Press Any Key to Continue Press any key to break test Capture frame buffer is full. Received Frame Count is %d Capture All Rx Frame Data Capture My Rx Frame Data Capture Matched Destination Rx Frame Data Enter Destination Address : Capture Broadcast Rx Frame Data Capture Control Rx Frame Data Capture & ShowFrame MAC Frame. [A] Capture All MAC Frame to Buffer Full. [M] Capture My MAC Address Frame. [B] Capture Broadcast Frame. [C] Capture Control Frame. [D] Capture Matched Destination Address. [S] Show Captured MAC Frame. [Q] Quit Show & Capture. MAC TEST [C] Capture & Show Ethernet Frame. [L] MAC Loopback Test. [T] Transfer Ethernet Frame. [R] Receive Ethernet Frame. [H] MAC Tx Halt Request Test. [M] MAC Configuration. [B] BDMA Configuration. [P] PHY MII Station Management. [A] View & Change MAC Address. [Q] Quit Ethernet Test Press any key to Continue MAC Test Select Transmit(T) or Quit(Q) ? MAC Rx Frame : Good ( %d ), Error ( %d ) Current Frame Descriptor Pointer : %08x Frame Data Ptr : %08x Reserved Field : %08x Status and Frame Length : %08x Next Frame Descriptor : %08x BDMARXPTR : %08x BDMASTAT : %08x BDMARXCON : %08x BDMARXLSZ : %08x BDMARXBUF : %08x CAM Base : %08x CAMCON : %08x MACCON : %08x MACRXCON : %08x MACRXSTAT : %08x MAC Tx Frame : Good ( %d ) Current Frame Descriptor Pointer : %08x Next Frame Descriptor : %08x BDMATXPTR : %08x BDMATXCON : %08x BDMATXBUF : %08x MACTXCON : %08x MACTXSTAT : %08x EMISSCNT : %08x EPZCNT : %08x System Configuration ROM/Flash Bank 0 Data Bus Size is.BYTESHORTWORD System Manager Status Stall Enabled (SE)..............1(enabled)0(disabled) Cache Enabled (CE).............. Cache Mode (CM).................00 (4K SRAM, 4K CACHE)01 (0K SRAM, 8K CACHE)10 (8K SRAM, 0K CACHE)11 (unused) Write Buffer Enabled (WE).......1 (enabled)0 (disabled) Internal SRAM Base Address......0x%08x Special Register Bank Base Ptr..0x%08x Product Identifier..............0x%x Sync. DRAM Mode.................%d Clock control register CLKCON.....0x%08x Clock Divided Value.............0x%08x ROM bank 5 wait.................1 (enable)0 (disable) ROM bank 5 address/data bus Mux. Mux bus Address Cycle (tAC).....(00) 1 MCLK(01) 2 MCLK(02) 3 MCLK(unused) Test bit is set.................10 Read Only Base..................0x%08x Read Only End...................0x%08x Read Only Size..................0x%08x %d Read/Write Base.................0x%08x Read/Write End..................0x%08x Read/Write Size.................0x%08x %d ZI Base.........................0x%08x ZI End..........................0x%08x ZI Size.........................0x%08x %d Max free DRAM region address=0x%08x size=%d Cache OFF %d.Cache tag Set0 Set1 10N March Test .... 8K Cache ON %d.Internal SRAM (4Kb mode) 10N March Test .... 4K Cache ON %d.Internal SRAM (8Kb mode) 10N March Test .... %d. Memory Test .... Source addr=0x%08x. Dest addr=0x%08x. Words=%d To skip test press ESC Fail. Skipped. Ok. %d. UART Test .... %d. GDMA Channel 0/1 Test .... %d. HDLC Test .... %d. IIC Test .... All Test Finished All Test Error Report %-20s%12s%12s%12sCache OFF4K Cache ON8K Cache ONInternal SRAMOk Fail Skipped Memory TestUART TestTIMER TestDMA TestIIC TestMAC TestHDLC Test time = %d:%d:%d.%d Fail Ok S3C4530 TEST [V] View Configuration [C] Cache/SRAM Test [M] Memory Test [T] Timer Test [U] UART Test [I] Interrupt Test [L] MAC/Ethernet Test [H] HDLC Test [D] GDMA Test [S] I2C Test [G] I/O Port Functions [A] All Test [P] Program Download Select Test Item: No Test Item Selected Press Any Key to Continue %12s %08x %12s 10 %12s 10987654321098765432109876543210 %12s 3 2 1 Data bus width for: [ 1: 0] ROM/SRAM/FLASH bank 0 (DSR0)...[%x] [ 3: 2] ROM/SRAM/FLASH bank 1 (DSR1)...[%x] [ 5: 4] ROM/SRAM/FLASH bank 2 (DSR2)...[%x] [ 7: 6] ROM/SRAM/FLASH bank 3 (DSR3)...[%x] [ 9: 8] ROM/SRAM/FLASH bank 4 (DSR4)...[%x] [10:11] ROM/SRAM/FLASH bank 5 (DSR5)...[%x] [13:12] DRAM bank 0 (DSD0).............[%x] [15:14] DRAM bank 1 (DSD1).............[%x] [17:16] DRAM bank 2 (DSD2).............[%x] [19:18] DRAM bank 3 (DSD3).............[%x] [21:20] external I/O bank 0 (DSX0).....[%x] [23:22] external I/O bank 1 (DSX1).....[%x] [25:24] external I/O bank 2 (DSX2).....[%x] [27:26] external I/O bank 3 (DSX3).....[%x] [1:0] Page mode configuration (PMC)..[%x] 00 = Normal ROM 01 = 4-word page 10 = 8-word page 11 = 16-word page Internal error [3:2] Page address access time (tPA).[%x] 00 = 5 cycles 01 = 2 cycles 10 = 3 cycles 11 = 4 cycles Internal error [6:4] Programmable access cycle(tACC)[%x] 000 = Disable bank 001 = 2 cycles 010 = 3 cycles 011 = 4 cycles 100 = 5 cycles 101 = 6 cycles 110 = 7 cycles 111 = Reserved [19:10] ROM/SRAM/Flash base pointer...[%x] ..............................[%x] [29:20] ROM/SRAM/FLASH next pointer...[%x] [0] EDO mode(EDO) (note).........[%x] 0 = Normal DRAM (Fast page mode DRAM) 1 = EDO DRAM [2:1] CAS strobe time (tCS)........[%x] 00 = 1 cycle [3:3] CAS pre-charge time (tCP )...[%x] 0 = 1 cycle 1 = 2 cycles NOTE In SDRAM mode, this bit affect SDRAM cycle. tCS value [1] : 0 = 1 cycle, 1 = 2 cycle [6:4] Reserved ....................[%x] These bits default value is 000. But, you must set to 001. [7] RAS to CAS delay(tRC or tRCD)[%x] 0 = 1 cycle 1 = 2 cycles Internal error [9:8] RAS pre-charge time (tRP) ...[%x] 00 = 1 cycle 01 = 2 cycles 10 = 3 cycles 11 = 4 cycles [19:10] DRAM bank # base pointer ....[%x] [%x] [29:20] DRAM bank # Next pointer ....[%x] [%x] [31:30] Number of column bits (CAN)..[%x] 00 = 8 bits 01 = 9 bits 10 = 10 bits 11 = 11 bits%s [9:0] External I/O base address ...[%x] .............................[%x] [15] Validity of special reg(VSF).%s1(Accessible to memory bank)0(Not accessible to memory bank) [16] Refresh enable (REN) ........%s1(Enable DRAM refresh)0(Disable DRAM refresh) [19:17] CAS hold time(tCHR)..........000 = 1 cycle001 = 2 cycles010 = 3 cycles011 = 4 cycles100 = 5 cycles101 = Not used (6 cycles) Not used NOTE : In EDO/normal DRAM mode, CAS hold time can be programmed upto 5 cycles. But in SDRAM mode, this bit fields function are defined as ROW Cycle Time (tRC) and can be programmed upto 6 cycles. [20] CAS setup time(t CSR)........1(2 cycles)0(1 cycle) NOTE : In SDRAM mode, this bit field is reserved. [31:21] Refresh count value (duration) ...[%x] The refresh period is calculated as (2 ** 11 - Value + 1) / fMCLK [31:21] Refresh period (us) ..............[%d] EXTCON%d 0x%08x [0:2] Chip selection set-up time on nOE %s=%dtCOS2tCOS0 [5:3] Address set-up time before nECS %s=%dtACS2tACS0 [8:6] Chip selection hold time on nOE %s=%dtCOH2tCOH0 [11:9] Access cycles nOE low time %s=%dtACC2tACC0 [18:16] Chip selection set-up time on nOE %s=%dtCOS3tCOS1 [21:19] Address set-up time before nECS %s=%dtACS3tACS1 [24:22] Chip selection hold time on nOE %s=%dtCOH3tCOH1 [27:25] Access cycles nOE low time %s=%dtACC3tACC1 ROM/DRAM Configuration [W] EXTDBWTH External data bus width register. [0] ROMCON0 ROM/SRAM/FLASH bank 0 register. [1] ROMCON1 ROM/SRAM/FLASH bank 1 register. [2] ROMCON2 ROM/SRAM/FLASH bank 2 register. [3] ROMCON3 ROM/SRAM/FLASH bank 3 register. [4] ROMCON4 ROM/SRAM/FLASH bank 4 register. [5] ROMCON5 ROM/SRAM/FLASH bank 5 register. [A] DRAMCON0 DRAM bank 0 control register. [B] DRAMCON1 DRAM bank 1 control register. [C] DRAMCON2 DRAM bank 2 control register. [D] DRAMCON3 DRAM bank 3 control register. [R] REFEXTCON. [E] EXTACON0. [X] EXTACON1. [Q] Quit. Select test item EXTDBWTHROMCON0ROMCON1ROMCON2ROMCON3ROMCON4ROMCON5DRAMCON0DRAMCON1DRAMCON2DRAMCON3REFEXTCON Press any key to continue Memory from 0x%08x to 0x%08x out of configured memory 0x%08x 0x%08x ROMCON0 ROMCON1 ROMCON2 ROMCON3 ROMCON4 ROMCON5 DRAMCON0 DRAMCON1 DRAMCON2 DRAMCON3 Press Any Key %08x : %02x Input Memory Dump Base Address (0x%08x) : 0x Input Memory Dump Size (0x100) : 0x Continue dump [Y/N]_ Memory Dump from %x to %x Memory Pattern Fill Memory Pattern Fill Start Address : 0x Memory Pattern Fill End Address : 0x Memor Fill Pattern (word) : 0x Memory region 0x%08x 0x%08x out of configured memory Memory Fill %08x to %08x, Pattern : %08x [Y/N]_ Memory Pattern Search Memory Pattern Search Start Address : 0x Memory Pattern Search End Address : 0x Memory Search Pattern (word) : 0x Continue Search [Y/N]_ Memory Pattern Search 0x%08x to 0x%08x, Pattern : %08x Pattern is Searched : 0x%08x (0x%08x) Memory Byte Test Error Source Data is %02x at Addr %08x Destin Data is %02x at Addr %08x Memory Short Test Error Source Data is %04x at Addr %08x Destin Data is %04x at Addr %08x Memory Long Test Error Source Data is %08x at Addr %08x Destin Data is %08x at Addr %08x Memory Test (Long)....Fail.Ok. Memory Test (Short) .. Memory Test (Byte) ...Ok Memory Copy Test Input Memory Test Source Location (0x01300000) : 0x Input Memory Test Destination Location(0x01400000): 0x Input Memory Test Size (word) (0x10000) : 0x Input Memory Test repeat number(0x00005) : 0x Source Memory Location : 0x%08x Destination Memory Location : 0x%08x Memory Test Size (words) : 0x%08x Memory Test Loop Count : %d Fail. Ok. External I/O Bank Test External I/O Bank #0 Base Addr : 0x%08x External I/O Bank #1 Base Addr : 0x%08x External I/O Bank #2 Base Addr : 0x%08x External I/O Bank #3 Base Addr : 0x%08x Test External I/O Bank source address (0x%08x)_0x Test External I/O Bank size (words) (0x%08x) _0x Configure External I/O Bank Bus Width [Y/N]_ External I/O Bank 0 Bus Width [D]isable/[B]yte/[H]alf word/[W]ord (%c)_ External I/O Bank 1 Bus Width [D]isable/[B]yte/[H]alf word/[W]ord (%c)_ External I/O Bank 2 Bus Width [D]isable/[B]yte/[H]alf word/[W]ord (%c)_ External I/O Bank 3 Bus Width [D]isable/[B]yte/[H]alf word/[W]ord (%c)_ EXTDBWTH = 0x%08x Select Test External I/O Bank (0, 1, 2, 3, Q) _ Invalid External I/O Bank Selected [%c] Configure External I/O Bank %c [Y]es/[N]o/[D]efault/[A]ll/[Q]uit]? Bank %d Chip selection set-up time on nOE tCOS%d (0-7)_ Invalid tCOS%d %c Bank %d Address set-up time before nECS tACS%d (0-7)_ Invalid tACS%d %c Bank %d Chip selection hold time on nOE tCOH%d (0-7) _ Invalid tCOH%d %c Bank %d Access cycles (nOE low time) tACC%d (0-7) _ External I/O Bank #0 Test External I/O Bank #1 Test External I/O Bank #2 Test External I/O Bank #3 Test Invalid External I/O Bank Selected Memory Test [V] View Memory Configuration [C] Memory Copy Test [R] Memory Dump [F] Memory Pattern Fill [S] Memory Pattern Search [E] External I/O Bank Test [Q] Quit Select Test Item : Invalid Test Item Selected Press Any Key To Continue ....Invalid number [%d] [%c] (null)%d.%d.%d.%d Error [0x%08x] = 0x%08x. Must be 0x%08xSYSCFG0x%08xStall enable (SE)Cache enable (CE)Write enable (WE)Fixed priority (FP)00(4Kb SRAM, 4Kb cache)01(0Kb SRAM, 8Kb cache)10(8Kb SRAM, 0Kb cache)(s@sXs Cache mode (CM)(unknown)S3C4510S3C4510BS3C4530XS3C4530AProduct Identifier%s Tag(256words) Test by 10N march algorithm Fail. Ok. SET0(4k),SET1(4K) Cache memory clear Start Clear Cache SET0 ERROR. SET0[0x%x] = 0x%x Fail. SET0 Cache Memory Not Cleared. SET0 Cache Memory Cleared. Clear Cache SET1 ERROR. SET1[0x%x] = 0x%x Fail. SET1 Cache Memory Not Cleared. SET1 Cache Memory Cleared.Clear Cache Tag Ram Error. [0x%x] = 0x%x. Fail. Tag Ram Not Cleared. Tag Ram Cleared. SRAM(4K bytes) test by 10N march algorithm. SRAM(8K bytes) test by 10N march algorithm. Cache[SET1]4K bytes tested by 10N march algorithm. Cache Set0,4K bytes,tested by 10N march algorithm. Internal SRAM test. 8K SRAM test? If NO,default 4K SRAM tested?[Y/N] SRAM Address:0x%08x~0x%08x Error [0x%08x] == 0x%08x Cache Tag Ram cleared. Cache Configurations. Stall Enable? [Y/N] Write buffer Enable? [Y/N] Cache Mode 0. 4K-bytes SRAM, 4K-bytes Cache. 1. 0K-bytes SRAM, 8K-bytes Cache. 2. 8K-bytes SRAM, 0K-bytes Cache. Select number Cache Disabled Cache Enable? [Y/N] CPU Clock change. Enter Clock divider value 0x Not correct input divider = 0x%x Only one bit can be set in CLKCON[15:0] Used = 0x%x CPU clock frequency is %d.%d Mhz. Reset clkcon register?[Y/N] Now Clock changed CLKCON=0x%x Uart Board Rate & DRAM refresh cycle were changed automaitcally. UARTBRD0=0x%08x <- 0x%08x [%d] UARTBRD1=0x%08x <- 0x%08x [%d] REFEXTCON=0x%08x 0x%08x Entern Search Pattern. 0x Search in Cache Set0. Set 0 : Address = %08x, Data = %08x Search in Cache Set1.Set 1 : Address = %08x, Data = %08x Search in DRAM Bank 0 [Y/N]DRAM 0 : Address = %08x, Data = %08x Search in DRAM Bank 1 [Y/N] DRAM 1 : Address = %08x, Data = %08x Search in DRAM Bank 2 [Y/N] DRAM 0 : Address = %08x, Data = %08x Search in DRAM Bank 3 [Y/N]CLKCON (Clock control register)15:0 Clock Divided Value%x16 ROM bank 5 wait enable1017 ROM bank 5 address/data Mux en00(1 MCLK)01(2 MCLK)10(3 MCLK)11(unused){{{{ 19:18 Mux bus Address Cycle (tAC)20 ROM bank 5 wait 1 cycle delay21 ROM bank 4 wait enable22 ROM bank 4 wait 1 cycle delay23 ROM bank 3 wait enable24 ROM bank 3 wait 1 cycle delay25 ROM bank 2 wait enable26 ROM bank 2 wait 1 cycle delay27 ROM bank 1 wait enable28 ROM bank 1 wait 1 cycle delay29 ROM bank 0 wait enable30 ROM bank 0 wait 1 cycle delayTest bitEXTACON 0&10x%08x 0x%08x Chip selection set-up time on nOE (tCOS0, tCOS1, tCOS2, tCOS3)0:2 EXTACON0 tCOS0%d0:2 EXTACON1 tCOS218:16 EXTACON0 tCOS118:16 EXTACON1 tCOS3 Address set-up time before nECS (tACS0, tACS1, tACS2, tACS3)5:3 EXTACON0 tACS05:3 EXTACON1 tACS221:19 EXTACON0 tACS121:19 EXTACON1 tACS3 Chip selection hold time on nOE (tCOH0,tCOH1,tCOH2,tCOH3)8:6 EXTACON0 tCOH08:6 EXTACON1 tCOH224:22 EXTACON0 tCOH124:22 EXTACON1 tCOH2 Access cycles (nOE low time (tACC0,tACC1,tACC2,tACC3)11:9 EXTACON0 tACC011:9 EXTACON1 tACC227:25 EXTACON0 tACC127:25 EXTACON1 tACC2EXTDBWTH Data Bus Width Register0x%0x11(word)10(half word)01(byte)00(disable)External I/O bank 3External I/O bank 2External I/O bank 1External I/O bank 0DRAM bank 3DRAM bank 2DRAM bank 1DRAM bank 0ROM/SRAM/FLASH bank 5ROM/SRAM/FLASH bank 4ROM/SRAM/FLASH bank 3ROM/SRAM/FLASH bank 2ROM/SRAM/FLASH bank 1ROM/SRAM/FLASH bank 0 ROMCON%d 0x%08x%d=%08x1:0 Page mode configuration (PMC) 00/N 01/4w 10/8w 11/16 00=Normal ROM; 01=4-word page; 10=8-word page; 11=16-word page3:2 Page address access time (tPA) 00/5 01/2 10/3 11/4 00=5 CLK;01=2 CLK;10=3 CLK; 11=4 CLK6:4 Programmable access cycle (tACC) 000/D 001/2 010/3 011/4 100/5 101/6 110/7 111/R 000=Disable ;001=2 cycles;010=3 cycles;011=4 cycles) 100=5 cycles);101=6 cycles;110=7 cycles;111=Reserved)19:10 base pointer %04x29:20 next pointer DRAMCON 0x%08x0 EDO mode1/EDO0/norm00/1CLK01/2CLK10/3CLK11/4CLK2:1 CAS strobe time (tCS)3:3 CAS precharge time (tCP)1=2CLK0=1CLK7 RAS to CAS delay(tRC or tRCD)00=1CLK01=2CLK10=3CLK11=4CLKĄ̄9:8 RAS pre-charge time (tRP)19:10 DRAM bank base pointer %-*x29:20 DRAM bank next pointer 00= 8bits01= 9bits10=10bits11=11bits\h@t31:30 Number of column bits (CAN) REFEXTCON=0x%08x9:0 External I/O bank 0 base pointer%04x15 Validity of special reg field(VSF)16 Refresh enable (REN)000=1 cycle001=2 cycles010=3 cycles011=4 cycles100=5 cycles101=6 cycles\hx 19:17 ROW Cycle Time20 CAS setup time(t CSR)1=2 cycles0=1 cycle31:21 Refresh count value (duration) [S] SYSCFG - System Configuration Register. [C] CLKCON - Clock Control Register. [E] EXTACON 0&1 - External I/O access timing register 0,1. [W] EXTDBWTH - Data bus width of each bank. [R] ROMCON0-5 - ROM/SRAM/FLASH control register 0,1,2,3,4,5 . [D] DRAMCON0-3 - DRAM control registers 0,1,2,3. [F] REFEXTCON [Q] Quit. Select Test Item: Press any key to continue. KS32C50100 CACHE & SRAM TEST [1] Tag RAM(256words) 10N march test. [2] Internal SRAM(4kbytes) 10N march test. [3] Internal SRAM(8kbytes) 10N march test. [4] Cache Set0(4kbytes) 10N march test. [5] Cache Set1(4kbytes) 10N march test. [6] Internal SRAM R/W test at 4k or 8k mode. ->SRAM address used as data pattern. [7] Cache start up dialog for setup cache mode. [8] Cache configuration. [9] Change CPU Clock use by clkcon register. [C] Cache Memory(SET0[4k]/SET1[4k]) Clear function. [B] Pattern search in cache memory region. [V] System registers (SYSCFG, CLKCON, ROMCON...). [A] All 10N March Test. [Q] QUIT - Return main menu. Cache configurations. Tag(256words) 10N March Test ..... Fail.Ok. SRAM(4K bytes) 10N March Test ..... SRAM(8K bytes) 10N March Test ..... Cache[SET1]4K bytes 10N March Test ..... [CACHE:ERROR] SET1[0x%x] = 0x%x!! Cache[SET0]4K bytes 10N March Test ..... [CACHE:ERROR] SET0[0x%x] = 0x%x!! TIMER 0 Status Timer 0 enable..............%s1(enabled.0(disabled) Timer 0 Toggle mode.........%s1(toggle mode)0(interval mode) Timer 0 initial TOUT0 value.%s10 TDATA0......................0x%08x TCNT0.......................0x%08x Timer0 TOUT0 output.(P16)...%senableddisabled Timer0 INT mode.............%sFIQIRQ Timer0 interrupt enabled....%s(disabled)(enabled) TIMER 1 STATUS Timer 1 enable..............%s Timer 1 Toggle mode.........%s Timer 1 Initial TOUT1 value.%s TDATA1......................0x%08x TCNT1.......................0x%08x Timer1 TOUT1 output.(P17)...%s1(enabled) Timer1 INT mode.............%s Timer1 interrupt enabled....%s Select timer[0/1] To exit, enter the Esc key on keyboard. To start timer press any key. TIMER1 timeTIMER0 time %s is %d:%d:%d.%d System hardware reset. Reset signal came from TOUT1 as reset input WatchDog Timer function test. Timer0 used as system timer. Timer1 used as watchdog timer. Watchdog timer counter value will be initialized at system timer interrupt service routine repeatedly. If you want to make the system hangup situation, Enter the character 'R'. Now, watchdog & system timer is running..... TIMER0 reconfigured with no watchdog Init function. Now, wathdog timer interrupt occurred... TIMER TEST [R] Running Timer 0,1. [W] Watchdog Timer function(Timer1) Test. [V] View the timer configurations. [Q] Type Q for exit timer test. Select Test Item: Press any key to continue. Rx error:sequence num=[tx %d rx %d] wait=[0x%02x] received=[0x%02x] UART 0&1 Internal Loopback Test Tx bytes=%d,%d, Rx bytes=%d,%d Errors=%d,%d UART%d External Loopback Test Rx error sended=[0x%02x] wait=[0x%02x] receive=[0x%02x] Tx bytes=%d, Rx bytes=%d, Errors=%d UART%d internal Loopback test (interrupt mode)... To break test press any key... Transmit bytes = [%d] Bytes sec = [%d] Receive bytes = [%d] Receive errors = [%d] Overrun errors = [%d] Parity errors = [%d] Frame errors = [%d] Break = [%d] Ok. Fail.  UART%d internal Loopback test (polling mode)... Fail. Tx bytes=[%d], Rx bytes=[%d],Err count=[%d] String echo for UART0 interrupt test.1 interrupt test. Select UART [0/1] Input characters will be echoed on Console To escape, enter ESC key : UARTLCON%d (UART%d line control register) = 0x%08x 1:0 Word length (WL)........00 = 5 bits01 = 6 bits10 = 7 bits11 = 8 bits 2 Number of Stop bits.....%s1(two Stop bits per frame)0(one Stop bit per frame) 5:3 Parity mode (PMD).......000(no parity)100(odd parity)101(even parity)110(parity is forced,checked as a 1)111(parity is forced,checked as a 0) 6 Serial Clock Selection..%s1(External UCLK)0(Internal MCLK) 7 Infra-red mode..........%s1(Infra-red Tx/Rx mode)0(Normal mode operation) UARTCONT%d UART%d Control Register = 0x%08x 1:0 Receive mode (RxM).................00(receive disabled)01(status int request)10(GDMA channel 0 req.)11(GDMA channel 1 req.) 2 Rx status interrupt enable (RxSI)..%s1(enable)0(disable) 4:3 Transmit mode (TxM)................00(transmit disabled)01(interrupt request) 5 Data set ready (DSR)...............%s10 6 Send break (SBK)...................%s 7 Loop-back mode (LPB)...............%s%s.%-15d%-*d%-*s(undef) UCON%d Control Register = 0x%08x UCON 0&1 Control Registers = 0x%08x 0x%08x00(disable)01(int req)10(GDMA0 req)11(GDMA1 req)ؚ̚1:0 Transmit mode (TMODE)ؚ̚ 3:2 Receive mode (RMODE)4 Send Break (SBR)5 Serial Clock Selection (UCLK)1(UCLK)0(MCLK)6 Auto Baud Rate Detect (ABRD)7 Look-back mode (LOOPB)1(loopback)0xx(no)100(odd)101(even)110(1)111(0)$0<D10:8 Parity mode (PMD)11 Number of Stop bits (STB)200(5 bits)01(6 bits)10(7 bits)11(8 bits)ĜМ ܜ013:12 Word Length (WL)14 Infra-red mode 15 Reserved16 Transmit FIFO enable (TFEN)17 Receive FIFO enable (RFEN)18 Transmit FIFO reset (TFRST)19 Receive FIFO reset (RFRST)00=30/3201=24/3210=16/3211=8/32 021:20 Tx FIFO trigger level (TFTL)..00 = 1/3201 = 8/3210 = 16/3211 = 24/32\h@t23:22 Rx FIFO trigger level (RFTL)..24 Data Terminal Ready to pin (DTR)25 Request to Send to pin (RTS).... 27:26 Reserved28 Hardware Flow Control En(HFEN)29 Software Flow Control En(SFEN) 31:30 Reserved UARTSTAT%d UART%d Status Register = 0x%08x 0 Overrun error..............%d 1 Parity error...............%d 2 Frame error................%d 3 Break interrupt............%d 4 Data terminal ready (DTR)..%d 5 Receive data ready.........%d 6 Tx Buffer register empty...%d 7 Transmit complete (TC).....%dUART%d status register=0x%08xUART 0&1 status registers=0x%08x,0x%08x0 Receive Data Valid (RDV)1 Break Signal Detected (BSD)2 Frame Error (FER)3 Parity Error (PER)4 Overrun Error (OER)5 Control Character Detect CCD)6 Data carrier Detect (DCD)7 Rx FIFO trigger level(RFREA)8 Receive FIFO empty (RFEMT)9 Receive FIFO full (RFFUL)10 Receive FIFO overrun (RFOV)11 Receiver in idle (RIDLE)12 Rx Event time out (E_RxTO) 13 Reserved Not applicable14 Data Set ready (DSR)15 Clear To Send (CTS)16 CTS Event occurred (E_CTS)17 Transmit Complete (TC)18 Tx Holding Reg Empty (THE)19 Transmit FIFO Empty (TFEMT)20 Transmit FIFO full (TFFUL) 31:21 ReservedUART%d int enable register=0x%08xUART 0&1 int enable registers=0x%08x,0x%08x0 Receive Data Valid(RDVIE)1 Break Signal Detected(BSDIE)2 Frame Error(FERIE)3 Parity Error(PERIE)4 Overrun Error(OERIE)5 Control Char Detect(CCDIE)6 DCD High at check time(DCDLIE)7 Rx FIFO trigger lev(RFREAIE) 9:8 Reserved10 Receive FIFO overrun(OVFFIE) 11 Reserved12 Rx Event timeout(E_RxTOIE) 15:13 Reserved16 CTS Event occurred(E_CTSIE) 17 Reserved18 Tx Holding Reg Empty(THEIE) 31:19 Reserved UARTBRD%d UART%d Baud Rate Divisor Register = 0x%08x 3:0 Baud rate divisor value CNT1......%d%(divide by 1)(divide by 16) 15:4 Time constant value for CNT0......%d BRGOUT = MCLK2/(CNT0+1)/(16^CNT1)/16...%d Set UART%d baudrate Current UART%d baud rate....%d Input new baud rate (38400). CNT0......%d CNT1......%d UARTBRD = 0x%08x BRGOUT = MCLK2 / (CNT0 + 1) / 16 ** CNT1 / 16 BRGOUT....%d [0] Change CNT0. [1] Change CNT1. [S] Set UARTBRD%d. [Q] Quit. Select Item Input CNT0 Input CNT1 [1] Toggle UART0 DSR. [2] Toggle UART1 DSR. [3] UART0 Send Break. [4] UART1 Send Break. Quit Select Item : UART0 & UART1 Configuration S3C4530 [C] UCONT0 - UART0 Control Register. UCONT1 - UART1 Control Register.KS32C50100 [L] UARTLCON0 - UART0 Line Control Register. UARTLCON1 - UART1 Line Control Register. [C] UARTCONT0 - UART0 Control Register. UARTCONT1 - UART1 Control Register). [B] UARTBRD0 - UART0 Baud Rate Divisor Register. UARTBRD1 - UART0 Baud Rate Divisor Register. [S] USTAT0 - UART0 Status Register. USTAT1 - UART1 Status Register. [I] UINTEN0 - UART0 Int Enable Register. UINTEN1 - UART1 Int Enable Register. [S] UARTSTAT0 - UART0 Status Register. UARTSTAT1 - UART1 Status Register. [Q] Quit [0] Set UART0 baudrate. [1] Set UART1 baudrate. Press any key to continue. UART 0&1 TEST [C] UART0 & UART1 configurations view & change. [0] URRT0 Internal Loopback test(POLL). [1] URRT1 Internal Loopback test(POLL). [2] URRT0 Internal Loopback test(INTERRUPT). [3] URRT1 Internal Loopback test(INTERRUPT). [4] URRT0 & UART1 Internal Loopback test(INTERRUPT). [5] UART0 String echo (INTERRUPT). [6] UART1 String echo (INTERRUPT). [7] UART0 External Loopback (INTERRUPT). [8] UART1 External Loopback (INTERRUPT). [Q] Quit - Return to main menu.$Id: zmodem.c,v 1.1.1.1 2001/03/08 00:01:48 efalk Exp $*ZSTDERRZCOMMANDZFREECNTZCANZCOMPLZCHALLENGEZCRCZFERRZEOFZDATAZRPOSZFINZABORTZNAKZSKIPZFILEZACKZSINITZRINITZRQINIT$Id: zmodemr.c,v 1.1.1.1 2001/03/08 00:01:48 efalk Exp $C$Id: zmodemt.c,v 1.1.1.1 2001/03/08 00:01:48 efalk Exp $rz noname OO Erase ROM bank 0. Base address 0x%08x Programm ROM bank 0 (#-1K writed). Fail. Address = [0x%08x]# Reset. Input Memory base address (0x%08x) 0xInput Memory size (%d) cancelled by user Select port UART0/UART1 [0/1/Q] Select Speed 38400/57600/115200 [3/5/1/Q]connect failed [%d] mem Sending: cannot open file filename [] too long, skipping... connect failed [%d] Start Programm at address 0x%08x [Y/N] Input base address (0x%08x) ZmRx UART%d Speed %d Base address 0x%08x connect failed [%d] File %s loaded Start address : 0x%08x File size : %d Program Download & Run [R] ZMODEM load & Run. [S] ZMODEM send. [G] Run User Program (loaded by command [R]). [F] Write flash & Reset. [X] Reset. [Q] Quit. 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